Alphanumeric LCD Display

Alphanumeric LCD display
Alphanumeric LCD display ADM0801C
Model No. ADM0801C
►alphanumeric LCD display
►Character LCD

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Product Details

Alphanumeric LCD display

Alphanumeric LCD display ADM0801C

Model No. ADM0801C

►alphanumeric LCD display

►Character LCD

►5 x 8 dots includes cursor

►Built-in controller ST7066

►5V power supply

►1/8 duty cycle

Description of alphanumeric LCD display ADM0801C

Searching for a display screen for a device or piece of equipment ? Alphanumeric LCD display from Amotec Display could be the perfect option. Available with various technologies and in customisable designs, Amotec's alphanumeric LCD display offers a practical and effective display solution.

Features

1.5x8 dots

2.Built-in controller (ST7066 or equivalent)

3.+5V power supply

4.Parallel interface input

5.1/8 duty

6.LED backlight Optional

7.8x1 character

Outline dimension

1.jpg

Absolute maximum ratings

Item

Symbol

Standard

Unit

Power voltage

VDD-VSS

-0.3

-

7.0

V

Input voltage

VIN

-0.3

-

VDD+0.3

Operating temperature range

Top

0

-

+50

Storage temperature range

Tst

-10

-

+60

*Wide temperature range is available

(operating/storage temperature as –20~+70/-30~+80℃)

Interface pin description

Pin no.

Symbol

External connection

Function

1

VSS

Power supply

Signal ground for LCM (GND)

2

VDD

Logic power supply for LCM

3

V0

Contrast adjust

4

RS

MPU

Register select signal

5

R/W

MPU

Read/write select signal

6

E

MPU

Operation (data read/write) enable signal

7~10

DB4~DB7

MPU

Four high order bi-directional three-state data bus lines.
Used for data transfer between the MPU

11~14

DB0~DB3

MPU

Four low order bi-directional three-state data bus lines.
Used for data transfer between the MPU and the LCM.
These four are not used during 4-bit operation.

15

A

LED+

Power supply for BKL+

16

K

LED-

Power supply for BKL-

Contrast adjust

2.jpg

VDD-V0: LCD Driving voltage

VR: 10k~20k

Optical characteristics

TN type display module (Ta=25℃, VDD=5.0V)

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

Viewing angle

θ

Cr≥4

-25

-

-

deg

Φ

-30

-

30

Contrast ratio

Cr


-

6

-

-

Response time (rise)

Tr

-

-

120

150

ms

Response time (fall)

Tr

-

-

120

150

STN type display module (Ta=25℃, VDD=5.0V)

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

Viewing angle

θ

Cr≥2

-60

-

35

deg

Φ

-40

-

40

Contrast ratio

Cr


-

8

-

-

Response time (rise)

Tr

-

-

200

250

ms

Response time (fall)

Tr

-

-

300

300

Electrical characteristics

DC characteristics

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Unit

Supply voltage for LCD

VDD-V0

Ta =25℃

-

4.6

-

V

Input voltage

VDD


2.7

-

5.5

Supply current

IDD

Ta=25℃, VDD=5.0V

-

1.5

2.5

mA

Input leakage current

ILKG


-

-

1.0

uA

“H” level input voltage

VIH


2.2

-

VDD

V

“L” level input voltage

VIL

Twice initial value or less

0

-

0.6

“H” level output voltage

VOH

LOH=-0.25mA

2.4

-

-

“L” level output voltage

VOL

LOH=1.6mA

-

-

0.4

Backlight supply voltage

VF


-

-

4.6

Read cycle (Ta=25℃, VDD=5.0V)

Parameter

Symbol

Test pin

Min.

Typ.

Max.

Unit

Enable cycle time

tc

E

500

-

-

ns

Enable pulse width

tw

230

-

-

Enable rise/fall time

tr, tf

-

-

20

RS; R/W setup time

tsu

RS; R/W
RS; R/W

40

-

-

RS; R/W address hold time

th

10

-

-

Data output delay

td

DB0~DB7

-

-

120

Data hold time

tdh

5

-

-

Write cycle

Parameter

Symbol

Test pin

Min.

Typ.

Max.

Unit

Enable cycle time

tc

E

500

-

-

ns

Enable pulse width

tw

230

-

-

Enable rise/fall time

tr, tf

-

-

20

RS; R/W setup time

tsu1

RS; R/W
RS; R/W

40

-

-

RS; R/W address hold time

th1

10

-

-

Data output delay

tsu2

DB0~DB7

80

-

-

Data hold time

th2

10

-

-

4.jpg

Instruction description

Outline

To overcome the speed difference between the internal clock of S6A0069 and the MPU clock, S6A0069 performs internal operations by storing control in formations to IR or DR. The internal operation is determined according to the signal from MPU, composed of read/write and data bus (Refer to Table7).

Instructions can be divided largely into four groups:

1)S6A0069 function set instructions (set display methods, set data length, etc.)

2)Address set instructions to internal RAM

3)Data transfer instructions with internal RAM

4)Others

The address of the internal RAM is automatically increased or decreased by 1.

Note: during internal operation, busy flag (DB7) is read “High”.

Busy flag check must be preceded by the next instruction.

When an MPU program with checking the busy flag (DB7) is made, it must be necessary 1/2 fuss for executing the next instruction by the falling edge of the “E” signal after the busy flag (DB7) goes to “LOW”.

Contents

1)Clear display


RS

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

0

0

0

0

0

0

0

0

1

Clear all the display data by writing “20H” (space code) to all DDRAM address, and set DDRAM address to “00H” into AC (address counter).

Return cursor to the original status, namely, brings the cursor to the left edge on the fist line of the display.

Make the entry mode increment (I/D=“High”).

2)Return home


RS

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

0

0

0

0

0

0

0

1

-

Return home is cursor return home instruction.

Set DDRAM address to “00H” into the address counter.

Return cursor to its original site and return display to its original status, if shifted.

Contents of DDRAM does not change.

3)Entry mode set

RS

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

0

0

0

0

0

0

1

I/D

SH

Set the moving direction of cursor and display.

I/D: increment / decrement of DDRAM address (cursor or blink)

When I/D=“high”, cursor/blink moves to right and DDRAM address is increased by 1.

When I/D=“Low”, cursor/blink moves to left and DDRAM address is increased by 1.

*CGRAM operates the same way as DDRAM, when reading from or writing to CGRAM.

(I/D=“high”. shift left, I/D=“Low”. Shift right).

4)Display ON/OFF control

RS

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

0

0

0

0

0

1

D

C

B

Control display/cursor/blink ON/OFF 1 bit register.

D: Display ON/OFF control bit

When D=“High”, entire display is turned on.

When D=“Low”, display is turned off, but display data remains in DDRAM.

C: cursor ON/OFF control bit

When D=“High”, cursor is turned on.

When D=“Low”, cursor is disappeared in current display, but I/D register preserves its data.

B: Cursor blink ON/OFF control bit

When B=“High”, cursor blink is on, which performs alternately between all the “High” data and display characters at the cursor position.

When B=“Low”, blink is off.

5)Cursor or display shift

RS

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

0

0

0

0

1

S/C

R/L

-

-

Shifting of right/left cursor position or display without writing or reading of display data.

This instruction is used to correct or search display data. (Refer to Table 6)

During 2-line mode display, cursor moves to the 2nd line after the 40th digit of the 1st line.

When display data is shifted repeatedly, each line is shifted individually.

When display shift is performed, the contents of the address counter are not changed.

Shift patterns according to S/C and R/L bits

S/C

R/L

Operation

0

0

Shift cursor to the left, AC is decreased by 1

0

1

Shift cursor to the right, AC is increased by 1

1

0

Shift all the display to the left, cursor moves according to the display

1

1

Shift all the display to the right, cursor moves according to the display

6)Function set

RS

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

0

0

0

1

DL

N

F

-

-

DL: Interface data length control bit

When DL=“High”, it mans 8-bit bus mode with MPU.

When DL=“Low”, it mans 4-bit bus mode with MPU. Hence, DL is a signal to select 8-bit or 4-bit bus mode.

When 4-but bus mode, it needs to transfer 4-bit data twice.

N: Display line number control bit

When N=“Low”, 1-line display mode is set.

When N=“High”, 2-line display mode is set.

F: Display line number control bit

When F=“Low”, 5x8 dots format display mode is set.

When F=“High”, 5x11 dots format display mode.

7)Set CGRAM address

RS

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

0

0

1

AC5

AC4

AC3

AC2

AC1

AC0

Set CGRAM address to AC.

The instruction makes CGRAM data available from MPU.

8)Set DDRAM address

RS

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

0

1

AC6

AC5

AC4

AC3

AC2

AC1

AC0

Set DDRAM address to AC.

This instruction makes DDRAM data available form MPU.

When 1-line display mode (N=LOW), DDRAM address is form “00H” to “4FH”.

In 2-line display mode (N=High), DDRAM address in the 1st line form “00H” to “27H”, and DDRAM address

In the 2nd line is from “40H” to “67H”.

9)Read busy flag & address

RS

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

BF

AC6

AC5

AC4

AC3

AC2

AC1

AC0

This instruction shows whether S6A0069 is in internal operation or not.

If the resultant BF is “High”, internal operation is in progress and should wait BF is to be LOW, which by then if the nest instruction can be performed. In this instruction you can also read the value of the address counter.

10)Write data to RAM

RS

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

1

0

D7

D6

D5

D4

D3

D2

D1

D0

Write binary 8-bit data to DDRAM/CGRAM.

The selection of RAM from DDRAM, and CGRAM, is set by the previous address set instruction (DDRAM address set, CGRAM address set).

RAM set instruction can also determine the AC direction to RAM.

After write operation. The address is automatically increased/decreased by 1, according to the entry mode.

11)Read data from RAM

RS

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

1

1

D7

D6

D5

D4

D3

D2

D1

D0

Read binary 8-bit data from DDRAM/CGRAM.

The selection of RAM is set by the previous address set instruction. If the address set instruction of RAM is not performed before this instruction, the data that has been read first is invalid, as the direction of AC is not yet determined. If RAM data is read several times without RAM address instructions set before, read operation, the correct RAM data can be obtained from the second. But the first data would be incorrect, as there is no time margin to transfer RAM data.

In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction,

It also transfers RAM data to output data register.

After read operation, address counter is automatically increased/decreased by 1 according to the entry mode.

After CGRAM read operation, display shift may not be executed correctly.

NOTE: In case of RAM write operation, AC is increased/decreased by 1 as in read operation.

At this time, AC indicates next address position, but only the previous data can be read by the read instruction.

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